View MDT10P4304_4909943.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MDT10P43 Spec
Ci 1. General Description
This 8-bit Micro-controller with built-in carrier generator uses a fully static CMOS technology to achieve high speed, small size, low power and high noise immunity. On chip memory includes 512 words of ROM, and 29 bytes of static RAM.
3. Applications
l Remote controller
4. Pin Assignment
P - PDIP, S - PSOP MDT10P43P21, MDT10P43S21
PA5 PA2 PA3 PA6 PA7 VSS PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA4 PA1 PA0 OSC1 OSC2 VDD PB7 PB6 PB5 PB4
2. Features
u u u u Fully COMS static design 8-bit data bus On chip ROM size : 512 words Internal RAM size : 28 bytes (24general purpose registers, 4 special registers) u u u u u 34 single word instructions 14-bit instructions 2-level stacks Operating voltage : 2.0V ~ 6 V Addressing modes include direct, indirect and relative addressing modes u u Power-on Reset System clock : 455KHz crystal (OSC1 cap 50P; OSC2 cap 100P) u PA0-7 : 8 input only pins with pull-high resistor and input low detect circuit. u u u PB0 : CMOS output. PB1 : 7 open drain output pins. Built in remote control carrier synthesizer Fosc/8 (56.9K) or Fosc/12 (37.9K) by firmware setting. u 2048 clocks for oscillator start up time.
MDT10P43P11, MDT10P43S11
PA2 PA3 PA6 PA7 VSS PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 PA1 PA0 OSC1 OSC2 VDD PB7 PB6 PB5 PB4
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 1 of 10 2004/12/2 Ver. 1.0
MDT10P43 Spec
5. Block Diagram
S ta c k T w o L e v e ls 9 bits
RO M 5 1 2 N 4 1 9 bits 14 bits I n s tr u c t io n R e g is t e r
R AM 2 4 N 8 P o rt A
Port PA0~PA 8 bits
P rog ra m C o u n t e rs
S pec ia l R eg is ter Port PB0 D0~D7 P o rt B I n s t r u c t io n D ec o d er C o n tr o l C ir c u it Data 8bit Port PB1~PB7
E xte rn al X T
P o w e r o n R e s et P ow e r D o w n R es e t W o rk in g R e g is t e r A LU S t a t u s R e g is t e r
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 2 of 10 2004/12/2 Ver. 1.0
MDT10P43 Spec
6. Pin Function Description
Pin Name PA0~PA7 I/O I Function Description Port A, TTL input level. Built in 50K ohm pull-high resistor. In sleep mode, a high-to-low change on any pin will cause chip reset. PB0 PB1~PB7 OSC1 OSC2 Vdd Vss O O I O CMOS output pin Port B open drain output pins, 50K ohm pull-high resistor. Crystal oscillation input pin Crystal oscillation output pin Power supply Ground
7. Memory Map
(A) Register Map Address 00 01 02 03 04 05 06 07 08~1F Description Indirect Addressing Register Unimplemented PC STATUS MSR Port A Unimplemented Unimplemented Internal RAM, General Purpose Register
(1) IAR ( Indirect Address Register) : R0
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 3 of 10 2004/12/2 Ver. 1.0
MDT10P43 Spec
(2) PC (Program Counter) : R2 Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTIW, RET --- from STACK
A9
A8
A7~A0
Write PC, JUMP, CALL --- from STATUS b5 LJUMP, LCALL --- from instruction word RTIW, RET --- from STACK Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTIW, RET --- from STACK (3) STATUS (Status register) : R3 Bit 0 1 2 3 4 5 6X7 Symbol C HC Z PF LPT XX XX Carry bit Half Carry bit Zero bit Power loss Flag bit Low power detect General purpose bit Carrier frequency control bits =00 No carrier (default) =01 Fosc/8, 1/2 duty =10 Fosc/12, 1/2 duty =11 Fosc/12, 1/3 duty (4) MSR (Memory Select Register) : R4 (5) PORT A : R5 Bit 7-0 : Port A data input (6) TRIS PB : Bit 7-1 : PB7-PB1 output register (open drain output) Bit 0 : PB0 output register (CMOS output) Function
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 4 of 10 2004/12/2 Ver. 1.0
MDT10P43 Spec
8. Reset Condition for all Registers
Register IAR PC STATUS MSR TRIS B Address 00h 02h 03h 04h 06h Power-On Reset 1111 1111 0001 1xxx 111x xxxx 1111 1110
Note : " x "xunknown, " - "xunimplemented, read as "0"
10. Instruction Set
Mnemonic Operands NOP SLEEP RET CPIO R STWR R LDR R, t LDWI I SWAPR R, t INCR R, t INCRSZ R, t ADDWR R, t SUBWR R, t DECR R, t DECRSZ R, t ANDWR R, t ANDWI i IORWR R, t IORWI i XORWR R, t XORWI i No operation Sleep mode Return Control I/O port register Store W to register Load register Load immediate to W Swap halves register Increment register Increment register, skip if zero Add W and register Subtract W from register Decrement register Decrement register, skip if zero AND W and register AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Exclu. OR W and register Exclu. OR W and immediate
Instruction Code 010000 00000000 010000 00000010 010000 00000100 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii
Function
Operating None 0/ WT, stop OSC Stack/ PC W/ CPIO r W/ R R/ t I/ W [R(0~3) R(4~7)]/ t R + 1/ t R + 1/ t W + R/ t R W/ t (R+/W+1/ t) R 1/ t R 1/ t R a W/ t i a W/ W R a W/ t i a W/ W R o W/ t i o W/ W
Status
TF, PF None None None Z None None Z None C, HC, Z C, HC, Z Z None Z Z Z Z Z Z
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 5 of 10 2004/12/2 Ver. 1.0
MDT10P43 Spec
Instruction Code 011111 trrrrrrr 010110 trrrrrrr Mnemonic Operands COMR R, t RRR R, t Function Complement register Rotate right register Operating /R/ t R(n) / R(n-1), C / R(7), R(0)/ C 010101 trrrrrrr RLR R, t Rotate left register R(n)/ r(n+1), C/ R(0), R(7)/ C 010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr 1000nn nnnnnnnn 1010nn nnnnnnnn 110000 nnnnnnnn 110001 iiiiiiii 11001n nnnnnnnn CLRW CLRR BCR BSR R R, b R, b Clear working register Clear register Bit clear Bit set Bit Test, skip if clear Bit Test, skip if set Long CALL subroutine Long JUMP to address Call subroutine Return, place immediate to W n JUMP to address 0/ W 0/ R 0/ R(b) 1/ R(b) Skip if R(b)=0 Skip if R(b)=1 n/ PC, PC+1/ Stack LJUMP n CALL RTIW JUMP n i n/ PC n/ PC, PC+1/ Stack Stack/ PC, i/ W n/ PC None None None None Z Z None None None None None C Status Z C
BTSC R, b BTSS R, b LCALL n
Note : W CPIO HC Z C PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Control I/O port register Half carry Zero flag Carry flag Power loss flag Program Counter Oscillator Inclusive `a ' Exclusive `o ' Logic AND `a ' b: t: Bit position Target 0 : Working register 1 : General register : : : : : General register address Immediate data ( 8 bits ) Immediate address Complement Don't care
R i n / x
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 6 of 10 2004/12/2 Ver. 1.0
MDT10P43 Spec
11. Electrical Characteristics
(Operating temperature at 25J ).
Sym
Description
Condition
Min 2.3
Typ
Max 5.5
Unit V
Vdd Operating voltage VIL Input Low Voltage PA VIH Input high Voltage PA IIL VOL Input leakage current Output Low Voltage PB Vdd=5V, IOL=20mA Vdd=5V, IOL=5mA VOH Output High Voltage PB0 Vdd=5V, IOH= -20mA Vdd=5V, IOH= -5mA Vpr Power Edge-detector Reset Voltage Vdd=5V Vdd=5V Vdd=5V
-0.6
1.0
V
2.0
Vdd +/-1
V
A
V V
0.5 0.2
4.0 4.7 1.5 1.9
V V V
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 7 of 10 2004/12/2 Ver. 1.0
MDT10P43 Spec
12. PA0 ~ PA7 Equivalent Circuit
I p tlow nu w e_u ak p
Sleep P 0~ P ll_H50K A 7: u i
D aBs at u
TL T I p tR n u esistor R ead TLI p tL T n u evel Pt or I p tP n u ad
13. (A) PB0 Equivalent Circuit
Carrier Fosc/12 Fosc/ 8 D TRIS Reset
Q DFFRA C Latch RB QB Port Output Pad
Data Bus Read
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 8 of 10 2004/12/2 Ver. 1.0
MDT10P43 Spec
(B) PB1~7 Equivalent Circuit
D TRIS Reset
Q DFFPA C Latch PB QB
PB1~7: Pull_Hi 50K
Port Output Pad Data Bus Read
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 9 of 10 2004/12/2 Ver. 1.0
MDT10P43 Spec
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 10 of 10 2004/12/2 Ver. 1.0

▲Up To Search▲

Price & Availability of MDT10P4304

	To Download MDT10P4304 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .